Nanotechnology For Electronics, Biosensors, Additive Manufacturing And Emerging Systems Applications by Jain Faquir C; Broadbridge C; Gherasimova M

Author:Jain, Faquir C; Broadbridge, C; Gherasimova, M
Language: eng
Format: epub
Publisher: World Scientific Publishing Company
Published: 2022-08-15T00:00:00+00:00

Fig. 2(a). Decoder.

Fig. 2(b). Schematic for Block ‘S’.

Fig. 3. Enhancement NMOS based (a) Nand (b) NOR and (c) Inverter.

Table I. Row decoder logic truth table

Method II: Alternatively, a second method for row/column decoder logic circuit that is more advantageous compared to method I is proposed. The truth-table to address each row/ column of a 4×4 and 12×12 DRAM crossbar array is shown in the Tables II and III respectively. Table II shows the truth table with two input combination bits for a 4×4 memory array and Table III shows the truth table for 12×12 array for 3-input bits. For each input bit increase, the array size increases 9 times. For a 3-input conventional MOS based 1-T, 1-C DRAM the array size is 8×8. Therefore, an SWSFET has 2.25 times the conventional DRAM. Extrapolating for an 8-bit input, conventional MOS DRAM has an array of 256×256 and SWSFET DRAM has 2916×2916 array. Therefore, the storage density increases by 129 times for 8-bit at the cost of increased metal lines and complex logic implementation.

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